% Circuit design
% <a href="http://stanford.edu/~boyd/papers/rc.html">Optimizing Dominant Time Constant in RC Circuits</a>
% <a href="http://stanford.edu/~boyd/papers/rc_iccad.html">Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology</a>
% <a href="http://stanford.edu/~boyd/papers/date05.html">Geometric Programming and its Applications to EDA Problems</a>
% <a href="http://stanford.edu/~boyd/papers/gp_digital_ckt.html">Digital Circuit Optimization via Geometric Programming</a>
%
%  wire_driver_sizing.m       - Combined sizing of drivers, repeaters, and wire
%  wire_sizing_spacing.m      - Combined wire sizing and spacing
%  dig_ckt_sizing.m           - Digital circuit sizing example (GP)
%  inverter_chain_sizing.m    - Digital circuit sizing for an inverter chain (GP)
%  elmore_straight_wire.m     - Elmore delay sizing for a straight wire (GP)
%  LC_osc_design.m            - LC oscillator design (GP)
%  wire_sizing.m              - Optimal interconnect wire sizing
%  clock_mesh.m               - Sizing of clock meshes
%  tristate_bus_sizing.m      - Tri-state bus sizing and topology design
%  simple_NAND2_gate_design.m - Two-input NAND gate sizing (GP)
%  wire_sizing_topology.m     - Wire sizing and topology design
%  simple_step.m              - Computes the step response of a linear system
%  plot_four_tapers.m         - Plots four different taper desings on a single graph.
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